October 10, 2023
Associate Professor Cynthia Sturton received two grants from the National Science Foundation to bolster hardware security verification. Both projects represent multi-institutional collaborations with broad applications.
The first grant, worth $1.2 million, is titled “Hardware Security Insights: Analyzing Hardware Designs to Understand and Assess Security Weaknesses and Vulnerabilities.” In collaboration with researchers at the University of California San Diego and Willamette University in Oregon, Sturton is working to develop better methods for understanding how information flows in computer hardware designs, with the intention of enhancing the security of that information.
Microprocessors, wireless modems, graphics processing units, and other hardware components at the heart of all computing devices are designed by engineers using hardware description languages. The designs are complex, making it difficult for others to reason about security vulnerabilities that may allow attackers to extract valuable information like cryptographic keys and personally identifiable information. Hardware security verification aims to identify hardware weaknesses, patch potential vulnerabilities, and mitigate the harm of attacks, and key to this aim is being able to understand how information flows in a hardware design.
Sturton’s project is structured around three primary goals that together will improve tools used for tracking and analyzing hardware information flow. The first goal is to be able to automatically generate information-flow properties. The second is to be able to test the full range of possible information flows through a design. The third is to develop a new “hyperflow analysis” framework that provides both analytic and visual representations to help verification engineers explore hardware vulnerabilities through an information-flow lens.
The project will give hardware engineers a set of automated tools to verify performance and security of models earlier into the design process.
The second grant is titled “A Hierarchical Machine Learning Approach for Securing of NoC-Based MPSoCs Against Thermal Attacks”. The project is a collaboration with researchers at North Carolina Agricultural and Technical State University and the University of Mississippi, incorporating machine learning and applicable to a broad range of computing systems using certain commercially available hardware.
The design of Multi-Processor System-on-Chips (MPSoCs) often involves the integration of pre-designed Intellectual Property (IP) components to minimize costs and accelerate time to market. This approach leaves room for potential manipulation of the manufacturing process by adversaries who insert malicious circuitry known as Hardware Trojans (HTs) into the final product. Depending on the intentions of the adversary, an HT can perform various malicious tasks, including compromising reliability, causing operational failures, leaking information, and initiating denial of services. The project is addressing security concerns related to HT-infected thermal sensors embedded in MPSoCs.
Thermal sensors are commonly used to regulate critical functions like power and operating temperature. Monitoring thermal sensors within an MPSoC allows for detection and isolation of compromised sensors. Thermal information is obtained from the cores on the chip and processed through a hierarchical series of machine learning classifiers ranging from small to complex. At each level, increasingly complex classifiers look for instances of compromised thermal sensors. The final and most complex level takes place in a cloud server, where the models are able to learn and provide feedback to improve the accuracy of the lower-level classifiers over time.
The project will help engineers and manufacturers limit security vulnerabilities, with the ability to improve detection over time as the model finds more and more examples of compromised sensors.