CSR–EHS Real-time Computing on Multicore Platforms

Principal Investigator: James H. Anderson
Funding Agency: National Science Foundation
Agency Number: CNS-0615197

Abstract
Thermal and power problems impose limits on the performance that single-processor chips can deliver. Multicore architectures (or chip multiprocessors), which include several processors on a single chip, are being widely touted as a way to circumvent this impediment. Several chip manufactures have released dual-core chips. Such chips include Intel’s Pentium~D and Pentium Extreme Edition, IBM’s PowerPC, AMD’s Opteron, and Sun’s UltraSPARC IV. A few designs with more than two cores have also been announced. For instance, Sun expects to ship its eight-core Niagara chip by early 2006. In addition, IBM recently introduced the Cell processor, which includes, on the same chip, a dual-core PowerPC plus eight “synergistic processing elements’ that are optimized for single- and double-precision mathematical calculations. Intel is expected to release four-, eight-, 16-, and perhaps even 32-core chips within a decade. Special-purpose multicore systems, such as network processors, have also been available for several years now. For software designs to take advantage of the parallelism available in these systems, careful attention must be paid to resource-allocation issues. For throughput-oriented applications, some initial work on such issues has been done. However, almost no such work has targeted real-time applications, which require very different resource-allocation methods, as they need performance guarantees. In this project, an approach will be investigated for synthesizing real-time applications on multicore systems. Both hard real-time applications, in which deadlines can never be missed, and soft real-time applications, in which some deadline misses are tolerable, will be considered. Examples of the former include control and tracking systems, and examples of the latter include multimedia and gaming systems. In multicore systems, care must be taken when scheduling and synchronizing tasks in order to avoid thrashing shared on-chip caches. In real-time systems, of course, real-time constraints must be ensured as well. The main objective of this project is to develop an allocation framework that addresses both concerns. Our main thesis is that such a framework should be based upon global real-time scheduling algorithms. Such algorithms are more flexible than the alternative, partitioning approaches. This flexibility yields two advantages. First, global algorithms are better able to use information about cache behavior to influence co-scheduling choices. Second, such algorithms (at least, those considered in this project) are immune from the bin-packing-like problems that plague partitioning approaches. In real-time systems, such problems can result in the need to place restrictive caps on overall utilization, wasting resources. Preliminary research suggests that the proposed framework, when fully deployed, will be flexible in its ability to ensure timing constraints, while encouraging low miss rates in shared caches. However, full deployment will require further work on several topics. The proposed research agenda includes research on these topics and an associated experimental evaluation. The proposed evaluation includes experiments with synthetically-generated real-time workloads on a multicore simulator, and experiments on an actual multicore platform involving multimedia workloads and also a human-tracking system used in immersive virtual environments. Broader impacts. With the ongoing shift to multicore technologies, this project could have a significant, far-reaching impact: in the future, multicore platforms will be the “standard’ computing platform in many settings, and real-time applications, many quite complex, will be deployed on them. Multicore platforms differ significantly from the kinds of platforms considered previously in work on real-time systems. This project, if funded, would be the first attempt within the real-time-systems research community to acknowledge these differences and to attempt to deal with them. The most direct impact of the proposed research on industry will likely be with respect to the design of operating-system components for future multicore products. Researchers at Intel, in particular, have expressed interest in our work, as evidenced by the attached supporting letter. We are hopeful that this interest will lead to collaborative efforts, summer internship possibilities for our students, etc. We also expect such interactions to lead to new collaborative research directions and to impact the content of several of our courses. Our research group has a good track record in involving graduate students from underrepresented groups, having graduated one female Ph.D. student last year, with a second expected this year. We expect this trend to continue. Public outreach will be accomplished by including the test-case systems developed in this project in our department’s long-running demo program. Any software of general utility that we produce will be made publically available on the web.

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